Test Beam Hints

This document contains hints for operation of the layer 2 SVT module which may be of use for the upcoming beam test

Typical current draws observed in the lab at UCSB were:

We have observed day-to-day shifts at the 20-30% level in the currents on the digital supplies; the reason is not understood. The currents on the analog supplies appear to be more stable.

With the old data transmission, the currents on the HDI Digital 5 supplies drop by ~ 200 mA when the clock is enabled. (The currents shown in the table above are with the clock enabled). With the new data transmission we think that this effect is smaller or absent (can't remember, sorry; maybe there is a reason for that ?).

The isolation voltages measured in Pisa for the two wafers of this detector are 30V and 12V. We have been operating it at 35V. The currents on these wafers have shown a strong sensitivity to ambient humidity. Therefore we reccomend circulating dry air (or equivalent) through the box that contains the detector.

It is a good idea to turn off the water flow if the HDI is powered down. This is to prevent the temperature from dropping too much and condensation to occur.

Remember

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To check that the matching card is properly connected to the hybrid, we have found it convenient to measure resistance between the differential command and clock pairs of lines at the signal connector on the matching card. Given the values of the terminating resistors, you should see a resistance of order 65 Ohms between these lines. For the data lines, you should expect to see of order 180 Ohms. This of course does not test that all the lines are properly connected, but it is a good sanity check.

When you perform the check described above, you will find that the resistance between the two Command B differential lines on the p-side is off. Do not panic. This is a known problem. We suspect that there is a bad connection between the Berg connector and the HDI substrate on one of these lines, probably because of a bad conductive-epoxy joint. It is therefore likely that the HDI will not work using the redundant Command/Clock B. Stick with Command/Clock A.

In our lab we terminated all lemo cables that carry signals from the data transmission to the ROM (i.e. data lines). We left all lemo cables that go from the ROM to the data transmission (i.e. clock and command lines) unterminated. Because there are a number of unmatched drivers and receivers in the system, we reccomend keeping the lemo cables as short as possible.

The masks for the chip at address 1 on the p-side are always read back as zeros. However, the chip behaves as if the masks are written correctly, so this chip is fully operational

The masks for the chip at address 6 on the n-side appear to be stuck in the OFF (zero) state. Therefore this chip is effectively dead.

There are two chips that behave strangely. They are at address 3 on the n-side and address 4 on the p-side. The problem is intermittent, and there is some indication that it can be fixed by power cycling. The symptom is that on approximately 20% of the events a very large number of channels on these chips fire together even when they are masked off (i.e. calibration masks = 0). In these events, all channels that fire report a time-over-threshold of 1, and the have the same time-stamp. The time-stamp varies randomly event by event. It sounds like a glitch at the output of the comparator or somewhere in the pipeline (?). There are a (small) number of channels on other chips that show a similar behavior. For some of them the problem is intermittent, and for some of them the problem is always there.